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Abdul Rasheed Kattubadi

Design Verification Engineer • Koilkuntla, Andhra Pradesh • k*********************@gmail.com • +91*******941 • drivetube.ai/•••••

Professional Summary

Design Verification Engineer with 0 years of experience focused on digital RTL verification and FPGA implementation using SystemVerilog, UVM and Verilog. Strong foundation in testbench architecture, assertion-based verification, constrained-random testing, functional coverage and FPGA RTL implementation. Seeking an entry-level verification role to apply academic projects and training experience toward IP/SoC verification assignments.

Technical Skills

Programming Languages: Shell scripting,C
Cloud and DevOps: Linux
Tools and Methodologies: Constrained-random verification,Functional coverage,Scoreboard & checkers,Assertion-based verification,Synopsys VCS,Verdi,Synopsys toolflow
Skills: Verilog,SystemVerilog,SystemVerilog Assertions SVA,UVM,Object-oriented programming OOPS
FPGA & RTL Implementation: Vivado,Xilinx Artix-7,RTL synthesis,Timing and resource analysis
Scripting & OS: TCL,AWK
Protocols & Buses: APB,UART
Design & Verification Practices: IP-level verification,Component and subsystem testbenches,Regression automation

Work Experience

Sumedha IT
Hyderabad, India
Design and Verification Trainee
July 2023 – March 2024
Design verification trainee supporting IP- and SoC-level verification learning tracks; worked on SystemVerilog/UVM testbenches and Synopsys simulation/debug toolflow.
Tech Stack: SystemVerilog, UVM, Verilog, Synopsys VCS, Verdi, TCL, Shell, AWK, Linux, SVA, Functional coverage
  • Designed and implemented modular UVM testbench components (agents, drivers, sequences, scoreboard) in SystemVerilog to verify IP blocks, improving reuse and enabling structured component-level regression.
  • Authored assertion checkers using SystemVerilog Assertions (SVA) to detect protocol and functional violations early in simulation, integrating assertions into the regression flow for continuous checking.
  • Developed constrained-random test sequences and functional-coverage models for APB and UART verification to exercise corner cases and measure verification completeness.
  • Executed RTL regressions and waveform debug using Synopsys VCS and Verdi; performed root-cause analysis of functional failures and iterated on test scenarios to isolate bugs.
  • Built component-level constrained-random verification (CRV) environments for IP verification, documented test plans and verification results to support traceability and handover.
  • Automated simulation runs, coverage collection and report aggregation with TCL and shell scripts (AWK) to streamline regression workflows and reduce manual effort during verification cycles.

Projects

FPGA-Based Fault-Tolerant Reversible ALU Design
Tools Used: Verilog, Vivado, Xilinx Artix-7, RTL design, Synthesis
  • Designed a reversible ALU architecture using hybrid IG–NFT gates to target low-power and quantum-compatible computing applications, implementing ADD, SUB, AND and XOR operations in Verilog RTL.
  • Optimized logic depth and propagation delay to reduce hardware overhead and improve performance for FPGA implementation.
  • Developed testbenches, performed RTL synthesis and implemented the design on Xilinx Artix-7 using Vivado; analyzed LUT utilization, timing and power.
  • Applied parity-preserving reversible logic to improve fault tolerance while minimizing resource usage compared to conventional reversible ALUs.
  • Validated functionality on FPGA and characterized performance gains; reported a 21.16% reduction in total power vs Fredkin–Feynman ALU and 34.80% vs Peres–HNG ALU.
Verification of FIFO using SystemVerilog
Tools Used: SystemVerilog, Testbench development, Assertions, Functional coverage
  • Developed a SystemVerilog simulation environment to validate FIFO functionality covering enqueue, dequeue, full and empty conditions.
  • Created directed and constrained-random scenarios to exercise boundary and stress cases of FIFO behavior.
  • Implemented SVA-based assertions to detect protocol and data integrity violations during simulation.
  • Added functional coverage points to quantify scenario coverage and identify untested FIFO corner cases.
  • Performed regression runs and waveform analysis to debug timing-related and functional issues in the FIFO RTL.
Verification of APB using UVM
Tools Used: UVM, SystemVerilog, Sequences, Drivers, Scoreboard
  • Built a UVM-based verification environment for APB protocol with monitor, driver, sequencer and scoreboard components.
  • Developed comprehensive read/write test sequences and corner-case scenarios to validate APB master/slave interactions.
  • Integrated protocol assertions and functional coverage to measure verification completeness for address, data and response fields.
  • Executed directed and randomized regressions to uncover interleaving and timing issues in APB transfers.
  • Used the scoreboard to compare expected vs observed transactions and to automate end-to-end data integrity checks.
Verification of UART using SystemVerilog
Tools Used: SystemVerilog, Verilog, Testbench design, Serial communication
  • Designed and implemented a UART-based serial communication system and corresponding verification testbench in SystemVerilog.
  • Created scenarios for transmission, reception, framing errors and baud-rate handling to verify UART robustness.
  • Developed firmware-style stimulus and monitor models to emulate microcontroller interactions with the UART interface.
  • Applied assertions to catch protocol violations and data corruption during transmission and reception.
  • Measured functional coverage for typical UART transactions and edge cases to identify untested behaviors.
Weapon Detection using Raspberry Pi and AI | January 2023 – July 2023
Tools Used: Raspberry Pi, Deep learning, Computer vision, Image processing
  • Built a weapon detection system leveraging a Raspberry Pi and a convolutional deep learning model to detect firearms in video streams.
  • Prepared and augmented a diverse image dataset and trained models to improve detection accuracy across varied scenarios.
  • Implemented real-time inference on the Raspberry Pi to trigger alerts when potential weapons were detected.
  • Used image-processing techniques to improve detection robustness in varied lighting and occlusion conditions.
  • Tested end-to-end performance on live video feeds and tuned pre- and post-processing to reduce false positives.

Education

Santhiram Engineering College, Nandyal
Master of Technology in VLSI (Electronics and Communication Engineering) • Nandyal, Andhra Pradesh • June 2024 – May 2026
Sri Venkateswara College of Engineering, Tirupati
Bachelor of Technology in Electronics and Communication Engineering • Tirupati, Andhra Pradesh • August 2020 – July 2023
E.S.C. Government Polytechnic, Nandyal
Diploma in Electronics and Communication Engineering • Nandyal, Andhra Pradesh • April 2017 – March 2020

Certifications

VLSI Design — Internshala • Aug 2022 - Sep 2022
Design and Verification — Sumedha IT, Hyderabad • Jul 2023 - Mar 2024

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