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Pagidi Pranavi

VLSI Design & Verification Engineer • Sullurupeta, Andhra Pradesh, India • p***************@gmail.com • +91*******366 • linkedin.com/••••• • drivetube.ai/•••••

Professional Summary

VLSI Design & Verification Engineer with internship experience in RTL design, FPGA development, and protocol-based IP verification using Verilog and Xilinx Vivado. Strong foundation in digital design, FSM implementation, AMBA protocols, and front-end RTL→simulation verification flows.

Technical Skills

Programming Languages: C,Python,MATLAB
Tools and Methodologies: Xilinx Vivado,Vivado Simulator,Quartus Prime,EDA Playground,Artix-7 Nexys A7,ZedBoard
Skills: Verilog HDL,RTL Coding
Design & Verification: Digital Design,RTL Design,Finite State Machines,Synthesis,Static Timing Analysis
Protocols: UART,SPI,I2C,APB,AXI,AXI4-Lite

Work Experience

ISRO, SDSC SHAR
Sriharikota, India
Intern
July 2025 – August 2025
Internship at ISRO's Satish Dhawan Space Centre; worked on FPGA-based RTL design and verification for protocol-compliant peripheral logic targeting ZedBoard.
Tech Stack: Verilog HDL, AXI4-Lite, Xilinx Vivado, ZedBoard, Synthesis, Static Timing Analysis
  • Implemented an AXI4-Lite Slave Up/Down Counter in Verilog for ZedBoard (Artix-7), designing parameterized registers and control signals for configurable data width and counters.
  • Implemented FSM-based control logic to manage AXI4-Lite read/write handshakes and ensured protocol compliance across address, read, and write channels using structured RTL coding.
  • Developed comprehensive directed and functional testbenches and executed simulations in Xilinx Vivado; validated read/write scenarios and corner cases, achieving 100% functionality verification in simulation.
  • Performed synthesis and applied timing constraints in Vivado to meet static timing on the Artix-7 platform; iterated RTL to resolve critical path issues and achieve timing closure.
  • Conducted on-board validation on the ZedBoard using Vivado logic analyzer and debug probes; identified and fixed timing/metastability issues to ensure reliable operation.
  • Prepared RTL deliverables, verification reports, and design documentation to support handoff and integration, describing interfaces, constraints, and test coverage.
Maven Silicon
Bengaluru, India
Intern
June 2025 – July 2025
VLSI design internship at a semiconductor training and IP-services company; focused on front-end RTL implementation and protocol-based IP verification.
Tech Stack: Verilog HDL, SPI, Xilinx Vivado, APB, Simulation, Synthesis
  • Designed and implemented an SPI Master IP core in Verilog with FSM-based control for clocking, data sampling, and chip-select management, supporting configurable data widths and clock polarity settings.
  • Created modular, parameterized RTL to allow variable data width and clock division, enabling reuse across different SPI configurations and target boards.
  • Built directed and constrained testbenches and performed simulations in Vivado to validate full-duplex transfers, edge cases, and timing relationships between MOSI/MISO/SCLK/CS signals.
  • Aligned SPI IP interfaces with AMBA front-end expectations (APB/AXI concepts exposure) and documented signal mapping and integration notes for system-level glue logic.
  • Executed synthesis runs in Vivado to analyze resource utilization and timing; applied RTL optimizations to reduce LUT/register use and meet target frequency.
  • Compiled verification reports, conducted peer code reviews, and presented the RTL→simulation→verification flow and lessons learned to mentors for feedback and readiness assessment.

Projects

Basic 5-Stage Pipelined Processor
Tools Used: Verilog HDL, Xilinx Vivado, RTL Design, Forwarding Logic
  • Implemented a RISC-style 5-stage pipeline (IF, ID, EX, MEM, WB) in Verilog with stage-wise module decomposition to improve instruction throughput.
  • Designed forwarding logic and hazard detection units to resolve data hazards and minimize pipeline stalls.
  • Verified functional correctness via Vivado simulation testbenches for a standard instruction set and branch scenarios.
  • Measured performance versus single-cycle design and achieved a 30% reduction in instruction latency through pipelining and forwarding optimizations.
UART Transmitter and Receiver
Tools Used: Verilog HDL, Vivado Simulator, UART, FSM Design
  • Designed FSM-based UART Tx and Rx modules in Verilog with configurable baud-rate generation and framing (start/stop/parity) logic.
  • Developed testbenches to validate start/stop bit detection, parity handling, and baud rate accuracy under varying clock domains.
  • Simulated and validated the design in Vivado; performed FPGA testing to ensure reliable serial communication with zero-bit error rate during verification runs.
Synchronous FIFO
Tools Used: Verilog HDL, Xilinx Vivado, FIFO Design, Pointer-Based Addressing
  • Implemented a parameterized synchronous FIFO with pointer-based read/write addressing, full/empty flag generation, and configurable depth.
  • Designed control logic to prevent overflow/underflow and ensure safe data synchronization between producer and consumer domains.
  • Modularized RTL for reusability and performed simulations in Vivado to validate throughput and corner-case behavior.
  • Optimized RTL architecture to reduce resource utilization by 20% through modular design and efficient pointer logic.

Education

Sri Venkateswara College of Engineering, Tirupati
Bachelor of Technology in Electronics and Communication Engineering • Tirupati, Andhra Pradesh, India • 2022 – Present
Sri Prathibha Junior College, Sullurupeta
Intermediate (Andhra Pradesh State Board of Intermediate Education) • Sullurupeta, Andhra Pradesh, India • 2020 – 2022
Tiny Tots E.M High School, Sullurupeta
Secondary Education (Andhra Pradesh State Board of Secondary Education) • Sullurupeta, Andhra Pradesh, India • 2019 – 2020

Certifications

VLSI Design Internship — SNARYS Technologies • May–June 2024
Complete Python Bootcamp — Udemy • May 2024
Linux Fundamentals (RH104) — Red Hat Academy • Jan 2025
National Coding League — Scalar • May 2024

Achievements

  • Member – IETE Student Branch — 2022–Present: Active member participating in technical sessions and departmental activities.
  • Volunteer – Annual Tech Symposium — 2022–2023: Coordinated event logistics and supported workshop sessions during the college tech symposium.

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