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G HIMAJA

RTL Design and Verification Engineer • Banglore • g**************@gamil.com • +91*******121 • drivetube.ai/•••••

Career Objective

RTL Design and Verification Engineer with 0 years of experience in RTL coding and verification using Verilog and SystemVerilog. Strong foundation in digital design, APB protocol implementation, constrained-random testbench development, assertions, functional coverage and simulation using QuestaSim; seeking entry-level RTL design/verification roles in semiconductor engineering.

Education

RGUKT RKVALLEY
Bachelor of Engineering • Kadapa, AP • 2021 – 2025

Technical Skills

Programming Languages: Python,C
Testing: Unit Testing
Tools and Methodologies: QuestaSim,EDA Playground,Gvim
Skills: Verilog,SystemVerilog
Protocols: APB,AMBA
Design & Verification Concepts: Digital Design,RTL Design,Testbench Development,Constraint-random Verification,Assertions,Functional Coverage,Debugging,Finite State Machines,Synchronous Counters

Projects

Design of APB Master | March 2026 – April 2026
Tools Used: Verilog, SystemVerilog, APB, Testbench Development, QuestaSim
  • Implemented APB master RTL in Verilog following AMBA APB specification to interface low-bandwidth peripherals for a microcontroller-style bus.
  • Designed and coded finite-state machine for APB transaction sequencing (address, write/read, enable phases) to ensure correct timing and handshake behavior.
  • Developed SystemVerilog testbench covering write/read transactions, setup/hold timing checks and error scenarios to validate protocol compliance.
  • Used QuestaSim for simulation and waveform inspection to locate and debug protocol timing issues and corner-case behavior during transaction retries.
  • Executed unit testing of the top module and iterated RTL based on simulation feedback to improve stability and reduce functional failures in edge cases.

Certifications

Professional Training – VLSI First (Digital & Verification) — VLSI First, Bangalore • Jan 2026 - Present

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