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B Tejaswara Rao

VLSI Design Verification Engineer • Bangalore, India • t********@gmail.com • +91*******876 • linkedin.com/••••• • drivetube.ai/•••••

Professional Summary

VLSI Design Verification Engineer with 0 years of experience delivering UVM-based verification environments and protocol-level verification for AMBA (AXI4/AHB/APB) DUTs. Trained in SystemVerilog/UVM and SVA with hands-on experience using Cadence Xcelium and SimVision, automated regression using TCL/Python, and hardware validation exposure from satellite payload checkout at VSSC/ISRO.

Technical Skills

Programming Language: Python,Verilog,Tcl,LabVIEW
Version Control & Development Tools: FSM Design,Sequential Logic,Combinational Logic,Gate-Level Concepts
Testing & QA: Code Coverage,Regression Testing
Project Management & Collaboration: SimVision
Hardware Design & Verification: SystemVerilog,UVM,SVA,Constrained Random Verification,Functional Coverage,Directed Testing,AMBA AXI4,AXI4-Lite,RTL Design
Communication Protocols: AHB,APB,UART
EDA & Simulation Tools: Cadence Xcelium,Xilinx Vivado

Work Experience

Maven Silicon
Bengaluru
DV Trainee — VLSI Design & Verification Program
Aug 2024 – Present
Training program focused on VLSI design verification; built end-to-end UVM environments and exercised AMBA protocol DUTs using Cadence simulation and waveform tools.
Tech Stack: SystemVerilog, UVM, SVA, Cadence Xcelium, SimVision, TCL, Python, AMBA AXI4, AHB, APB, Xilinx Vivado
  • Architected end-to-end UVM testbenches (uvm_test → uvm_env → uvm_agent → sequencer/driver/monitor/scoreboard) for AMBA AXI4, AHB, and APB DUTs using SystemVerilog; authored constrained-random and directed sequences and achieved 95%+ functional coverage across training DUTs.
  • Defined coverage-driven verification strategy with SystemVerilog covergroups and functional coverage plans; tracked line/toggle/branch/FSM code coverage in Cadence Xcelium to drive closure and prioritize debug targets.
  • Implemented SVA-based protocol checkers for VALID/READY and bus-transfer properties; integrated assertion monitoring into regression runs to surface latent RTL protocol violations early in the cycle.
  • Debugged functional failures using SimVision waveform analysis and log tracing; isolated scoreboard mismatches by cross-referencing DUT outputs with golden models and assertions, reducing time-to-root-cause during sign-off cycles.
  • Automated nightly regression runs, report generation and result parsing using TCL for batch simulation control and Python for log parsing; reduced manual regression overhead and accelerated coverage convergence across configurations.
  • Prepared and maintained regression suites and sign-off reports across DUT variants; coordinated coverage closure activities and ensured repeatable simulation workflows for final verification sign-off.
VSSC / ISRO
Thiruvananthapuram
Intern — Satellite Payload Checkout
Jan 2024 – Mar 2024
Hardware validation and payload checkout at ISRO's VSSC; executed functional and interface validation across embedded payload subsystems using LabVIEW-based test automation.
Tech Stack: LabVIEW, UART
  • Executed functional validation of satellite payload embedded subsystems across Analog, Digital, Power, Avionics, IF and RF domains; followed structured payload checkout procedures to verify subsystem readiness for integration.
  • Developed and executed LabVIEW-based test sequences to verify signal integrity, power consumption thresholds and inter-subsystem communications, reducing manual test cycles and improving repeatability.
  • Implemented and validated UART-based communication tests on embedded hardware to verify framing, timing and error-free transmission under operational test conditions.
  • Performed telemetry/telecommand (TM/TC) interface verification and assisted in payload certification compliance checks to ensure adherence to mission test requirements.
  • Captured and analyzed test logs and waveform traces to isolate hardware/firmware interaction issues; documented findings and collaborated with system engineers to drive corrective actions.
  • Automated data capture and test reporting in LabVIEW to accelerate test throughput and provide reproducible evidence for payload acceptance activities.
National Technology

Projects

AXI4 Full Master–Slave Verification — UVM Testbench | In Progress
Tools Used: SystemVerilog, UVM, AMBA AXI4, SVA, Cadence Xcelium, TCL
  • Designing a layered UVM environment for a full AXI4 Master–Slave IP covering all five channels (AW, W, B, AR, R); implementing interfaces and clocking blocks for synchronized stimulus.
  • Developing constrained-random UVM sequences to exercise INCR/WRAP burst types, outstanding transactions and out-of-order response scenarios, with integrated SVA checkers for continuous protocol compliance.
  • Defining a functional coverage plan across burst type, data width, response types and error injection scenarios and planning nightly regression automation via TCL on Cadence Xcelium.
Router 1×3 — RTL Design & UVM Verification
Tools Used: SystemVerilog, UVM, Cadence Xcelium
  • Built a full UVM verification environment for a 1×3 router RTL design with three destination FIFOs; implemented driver/monitor/scoreboard to validate dataflow and control signals.
  • Applied constrained-random stimulus to achieve 95%+ functional coverage across payload sizes 7–17 bytes; validated FIFO read/write behavior, gating and soft-reset across output ports.
  • Tracked line/toggle/branch coverage in Cadence Xcelium and debugged scoreboard mismatches by comparing DUT outputs with a golden model to eliminate false-pass scenarios.
AHB-APB Bridge — AMBA Protocol Verification using UVM
Tools Used: SystemVerilog, UVM, AHB, APB, SVA, Cadence Xcelium
  • Designed and verified an AHB-to-APB bridge with SystemVerilog interfaces and clocking blocks to ensure synchronized stimulus across bus domains.
  • Implemented layered UVM testbench with sequence-based constrained-random stimulus to drive AHB burst transactions and validated correct APB-side responses for normal, boundary and error scenarios.
  • Integrated functional coverage and SVA assertions for transfer-type and burst-length compliance; assertions surfaced two latent RTL bugs during simulation that were analyzed and reported.
Satellite Payload Checkout System — Hardware Validation (VSSC / ISRO)
Tools Used: LabVIEW, UART
  • Executed functional validation and hardware checkout activities spanning Analog, Digital, Power, Avionics, IF and RF test domains for satellite payload subsystems.
  • Verified signal integrity, power thresholds and inter-subsystem interfaces using LabVIEW-based automation and captured telemetry/telecommand traces for acceptance evidence.
  • Implemented UART protocol tests on embedded modules and validated reliable data framing and timing under operational scenarios.

Education

Sanketika Vidya Parishad Engineering College
B.E. — Electronics & Communication Engineering • 2024

Certifications

VLSI Design & Verification Training — Maven Silicon — Maven Silicon
SystemVerilog for Verification Engineers — Maven Silicon — Maven Silicon
Industrial Training — Vizag Steel Plant (Embedded systems exposure) — Vizag Steel Plant

Achievements

  • Selected by DRDO to present B.Tech final-year project at National Technology Day 2024 (NSTL, Ministry of Defence) — May 2024
  • Presented AXI4-Lite Verification project at a technical symposium: Demonstrated protocol coverage methodology and assertion-based debug strategy to an industry audience.
  • Outstanding Performance Award — Maven Silicon VLSI Design & Verification Program: Recognized across the cohort for technical depth and project execution.

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