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Narukulla Veda Sri

Graduate Engineer Trainee • Khammam, Telangana • n***************@gmail.com • +91*******735 • drivetube.ai/•••••

Career Objective

Graduate Engineer Trainee with 0 years of experience in digital design and prototype software for academic projects. Strong academic foundation in Electronics and Communication Engineering with hands-on project experience implementing a rule-based educational chatbot in Python and designing a power-efficient multi-operand adder using a binary-tree architecture in Verilog. Skilled in digital logic design, testbench-driven verification, algorithm design for binary-tree reduction, version control with Git, and basic NLP pattern matching for intent recognition. Comfortable performing logic simulation, functional verification, and simple post-synthesis analysis. Seeking an entry-level engineering role where I can apply hardware description languages, digital design techniques, and scripting to contribute to embedded systems or FPGA-based projects while continuing to learn industry tools and workflows.

Education

CMR Technical Campus, Medchal
Bachelor of Technology (Electronics and Communication Engineering) • Medchal, Telangana • 2022 – 2026
Krishnaveni Junior College, Khammam
Intermediate (TSBIE) • Khammam, Telangana
Good News E.M High School, Enkoor
Secondary School Certificate (SSC) • Enkoor, Telangana

Technical Skills

Programming Language: Python,Verilog
Version Control & Development Tools: Git,Digital Logic Design,Binary-tree Reduction Algorithms,Logic Simulation,Rule-based Intent Recognition,Regular Expressions
API & Integrations: JSON
Hardware Design & Verification: Testbench Development

Projects

Sci Chat for Scholars
Tools Used: Python, Regular Expressions, JSON, Rule-based Intent Recognition, Git
  • Implemented a prototype educational chatbot in Python to answer student academic queries using a rule-based intent-recognition approach.
  • Built keyword and pattern-matching modules with regular expressions to classify user intents and map queries to curated responses stored as JSON.
  • Designed conversational flow and response-selection logic to prioritize concise, relevant answers for STEM-focused FAQ content.
  • Developed unit test scripts to validate reply correctness across common query variations and edge cases.
  • Managed source code and version control using Git; produced README and inline documentation describing architecture and usage.
Power Efficient Multi Operand Adder using Binary Tree
Tools Used: Verilog, Digital Logic Design, Binary-tree Reduction Algorithms, Testbench Development, Logic Simulation
  • Designed a binary-tree based multi-operand adder architecture to reduce critical path depth compared with linear adder approaches.
  • Implemented the adder in Verilog with modular reduction stages and parameterizable operand width to support varying bit-sizes.
  • Developed comprehensive Verilog testbenches to verify functional correctness across corner cases and randomized input vectors.
  • Executed logic simulation to validate timing and behavior; iterated the design to reduce gate-level depth and resource usage.
  • Performed comparative analysis of logic depth and routeable complexity to demonstrate improved latency characteristics over ripple designs.

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